? semiconductor components industries, llc, 2013 june, 2013 ? rev. 16 1 publication order number: cat5112/d cat5112 32\tap digital potentiometer (pot) with buffered wiper description the cat5112 is a single digital pot designed as an electronic replacement for mechanical potentiometers. ideal for automated adjustments on high volume production lines, they are also well suited for applications where equipment requiring periodic adjustment is either difficult to access or located in a hazardous or remote environment. the cat5112 contains a 32-tap series resistor array connected between two terminals r h and r l . an up/down counter and decoder that are controlled by three input pins, determines which tap is connected to the wiper, r wb . the cat5112 wiper is buffered by an op amp that operates rail to rail. the wiper setting, stored in non-volatile memory, is not lost when the device is powered down and is automatically recalled when power is returned. the wiper can be adjusted to test new system values without effecting the stored setting. wiper-control of the cat5112 is accomplished with three input control pins, cs , u/d , and inc . the inc input increments the wiper in the direction which is determined by the logic state of the u/d input. the cs input is used to select the device and also store the wiper position prior to power down. the digital pot can be used as a buffered voltage divider. for applications where the potentiometer is used as a 2-terminal variable resistor, please refer to the cat5114. the buffered wiper of the cat5112 is not compatible with that application. features ? 32-position linear taper potentiometer ? non-volatile eeprom wiper storage; buffered wiper ? low power cmos technology ? single supply operation: 2.5 v ? 6.0 v ? increment up/down serial interface ? resistance values: 10 k , 50 k and 100 k ? available in pdip, soic, tssop and msop packages ? these devices are pb-free, halogen free/bfr free and are rohs compliant applications ? automated product calibration ? remote control adjustments ? offset, gain and zero control ? tamper-proof calibrations ? contrast, brightness and volume controls ? motor controls and feedback systems ? programmable analog functions http://onsemi.com pin configurations r h r wb r l u/d inc v cc cs 1 see detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. ordering information soic ? 8 v suffix case 751bd msop ? 8 z suffix case 846ad gnd pdip (l), soic (v), msop (z) pdip ? 8 l suffix case 646aa tssop ? 8 y suffix case 948al increment control inc up/down control u/d potentiometer high terminal r h ground gnd buffered wiper terminal r wb potentiometer low terminal r l function pin name pin function chip select cs supply voltage v cc tssop (y) (top views) gnd r h u/d inc r wb cs v cc r l 1
cat5112 http://onsemi.com 2 figure 1. functional diagram figure 2. electronic potentiometer implementation control and memory power on recall gnd + ? + ? u/d inc cs v cc r wb r h r l r wb r l r h pin description inc : increment control input the inc input (on the falling edge) moves the wiper in the up or down direction determined by the condition of the u/d input. u/d : up/down control input the u/d input controls the direction of the wiper movement. when in a high state and cs is low, any high ? to ? low transition on inc will cause the wiper to move one increment toward the r h terminal. when in a low state and cs is low, any high-to-low transition on inc will cause the wiper to move one increment towards the r l terminal. r h : high end potentiometer terminal r h is the high end terminal of the potentiometer. it is not required that this terminal be connected to a potential greater than the r l terminal. voltage applied to the r h terminal cannot exceed the supply voltage, v cc or go below ground, gnd. r wb : wiper potentiometer terminal (buffered) r wb is the buffered wiper terminal of the potentiometer. its position on the resistor array is controlled by the control inputs, inc , u/d and cs . r l : low end potentiometer terminal r l is the low end terminal of the potentiometer. it is not required that this terminal be connected to a potential less than the r h terminal. voltage applied to the r l terminal cannot exceed the supply voltage, v cc or go below ground, gnd. r l and r h are electrically interchangeable. cs : chip select the chip select input is used to activate the control input of the cat5112 and is active low. when in a high state, activity on the inc and u/d inputs will not affect or change the position of the wiper. device operation the cat5112 operates like a digitally controlled potentiometer with r h and r l equivalent to the high and low terminals and r wb equivalent to the mechanical potentiometer?s wiper. there are 32 available tap positions including the resistor end points, r h and r l . there are 31 resistor elements connected in series between the r h and r l terminals. the wiper terminal is connected to one of the 32 taps and controlled by three inputs, inc , u/d and cs . these inputs control a five-bit up/down counter whose output is decoded to select the wiper position. the selected wiper position can be stored in nonvolatile memory using the inc and cs inputs. with cs set low the cat5112 is selected and will respond to the u/d and inc inputs. high to low transitions on inc will increment or decrement the wiper (depending on the state of the u/d input and five-bit counter). the wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. the value of the counter is stored in nonvolatile memory whenever cs transitions high while the inc input is also high. when the cat51 12 is powered-down, the last stored wiper counter position is maintained in the nonvolatile memory. when power is restored, the contents of the memory are recalled and the counter is set to the value stored. with inc set low, the cat5112 may be deselected and powered down without storing the current wiper position in nonvolatile memory. this allows the system to always power up to a preset value stored in nonvolatile memory.
cat5112 http://onsemi.com 3 table 1. operation modes inc cs u/d operation high to low low high wiper toward r h high to low low low wiper toward r l high low to high x store wiper position low low to high x no store, return to standby x high x standby figure 3. potentiometer equivalent circuit c w r l c l c h r wb r wi r h table 2. absolute maximum ratings parameters ratings units supply voltage v cc to gnd ? 0.5 to +7 v inputs cs to gnd ? 0.5 to v cc +0.5 v inc to gnd ? 0.5 to v cc +0.5 v u/d to gnd ? 0.5 to v cc +0.5 v r h to gnd ? 0.5 to v cc +0.5 v r l to gnd ? 0.5 to v cc +0.5 v r wb to gnd ? 0.5 to v cc +0.5 v operating ambient temperature commercial (?c? or blank suffix) 0 to 70 ? c industrial (?i? suffix) ? 40 to +85 ? c junction temperature +150 ? c storage temperature ? 65 to +150 ? c lead soldering (10 s max) +300 ? c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. table 3. reliability characteristics symbol parameter test method min typ max units v zap (note 1) esd susceptibility mil ? std ? 883, test method 3015 2000 v i lth (notes 1, 2) latch-up jedec standard 17 100 ma t dr data retention mil ? std ? 883, test method 1008 100 years n end endurance mil ? std ? 883, test method 1003 1,000,000 stores 1. this parameter is tested initially and after a design or process change that affects the parameter. 2. latch-up protection is provided for stresses up to 100 ma on address and data pins from ? 1 v to v cc + 1 v
cat5112 http://onsemi.com 4 table 4. dc electrical characteristics (v cc = +2.5 v to +6 v unless otherwise specified) symbol parameter conditions min typ max units power supply v cc operating voltage range 2.5 ? 6 v i cc1 supply current (increment) v cc = 6 v, f = 1 mhz, i w = 0 ? ? 200 a v cc = 6 v, f = 250 khz, i w = 0 ? ? 100 a i cc2 supply current (write) programming, v cc = 6 v ? ? 1000 a v cc = 3 v ? ? 500 a i sb1 (note 4) supply current (standby) cs = v cc ? 0.3 v u/d , inc = v cc ? 0.3 v or gnd ? 75 150 a logic inputs i ih input leakage current v in = v cc ? ? 10 a i il input leakage current v in = 0 v ? ? ? 10 a v ih1 ttl high level input voltage 4.5 v ? v cc ? 5.5 v 2 ? v cc v v il1 ttl low level input voltage 0 ? 0.8 v v ih2 cmos high level input voltage 2.5 v ? v cc ? 6 v v cc x 0.7 ? v cc + 0.3 v v il2 cmos low level input voltage ? 0.3 ? v cc x 0.2 v potentiometer characteristics r pot potentiometer resistance ? 10 device 10 k ? 50 device 50 ? 00 device 100 pot. resistance tolerance ? 20 % v rh voltage on r h pin 0 v cc v v rl voltage on r l pin 0 v cc v resolution 1 % inl integral linearity error i w ? 2 a 0.5 1 lsb dnl differential linearity error i w ? 2 a 0.25 0.5 lsb r out buffer output resistance 0.05 v cc ? v wb ? 0.95 v cc , v cc = 5 v 1 i out buffer output current 0.05 v cc ? v wb ? 0.95 v cc , v cc = 5 v 3 ma tc rpot tc of pot resistance 300 ppm/ ? c tc ratio ratiometric tc 20 ppm/ ? c c rh /c rl /c rw potentiometer capacitances 8/8/25 pf fc frequency response passive attenuator, 10 k 1.7 mhz v wb(swing) output voltage range i out ? 100 a, v cc = 5 v 0.01 v cc 0.99 v cc 3. this parameter is tested initially and after a design or process change that affects the parameter. 4. latch-up protection is provided for stresses up to 100 ma on address and data pins from ? 1 v to v cc + 1 v 5. i w = source or sink 6. these parameters are periodically sampled and are not 100% tested.
cat5112 http://onsemi.com 5 table 5. ac test conditions v cc range 2.5 v ? v cc ? 6 v input pulse levels 0.2 v cc to 0.7 v cc input rise and fall times 10 ns input reference levels 0.5 v cc table 6. ac operating characteristics (v cc = +2.5 v to +6.0 v, v h = v cc , v l = 0 v, unless otherwise specified) symbol parameter min typ (note 7) max units t ci cs to inc setup 100 ? ? ns t di u/d to inc setup 50 ? ? ns t id u/d to inc hold 100 ? ? ns t il inc low period 250 ? ? ns t ih inc high period 250 ? ? ns t ic inc inactive to cs inactive 1 ? ? s t cph cs deselect time (no store) 100 ? ? ns t cph cs deselect time (store) 10 ? ? ms t iw inc to v out change ? 1 5 s t cyc inc cycle time 1 ? ? s t r , t f (note 8) inc input rise and fall time ? ? 500 s t pu (note 8) power-up to wiper stable ? ? 1 ms t wr store cycle ? 5 10 ms 7. typical values are for t a = 25 ? c and nominal supply voltage. 8. this parameter is periodically sampled and not 100% tested. 9. mi in the a.c. timing diagram refers to the minimum incremental change in the w output due to a change in the wiper position. figure 4. a.c. timing 90% 90% 10% (store) t r t f mi (3) t ic t cph t iw r wb u/d inc cs t ci t di t id t il t ih t cyc
cat5112 http://onsemi.com 6 package dimensions pdip ? 8, 300 mils case 646aa issue a e1 d a l eb b2 a1 a2 e eb c top view side view end view pin # 1 identification notes: (1) all dimensions are in millimeters. (2) complies with jedec ms-001. symbol min nom max a a1 a2 b b2 c d e e1 l 0.38 2.92 0.36 6.10 1.14 0.20 9.02 2.54 bsc 3.30 5.33 4.95 0.56 7.11 1.78 0.36 10.16 eb 7.87 10.92 e 7.62 8.25 2.92 3.80 3.30 0.46 6.35 1.52 0.25 9.27 7.87
cat5112 http://onsemi.com 7 package dimensions soic 8, 150 mils case 751bd issue o e1 e a a1 h l c e b d pin # 1 identification top view side view end view notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec ms-012. symbol min nom max a a1 b c d e e1 e h 0o 8o 0.10 0.33 0.19 0.25 4.80 5.80 3.80 1.27 bsc 1.75 0.25 0.51 0.25 0.50 5.00 6.20 4.00 l 0.40 1.27 1.35
cat5112 http://onsemi.com 8 package dimensions tssop8, 4.4x3 case 948al issue o e1 e a2 a1 e b d c a top view side view end view 1 l1 l notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec mo-153. symbol min nom max a a1 a2 b c d e e1 e l1 0o 8o l 0.05 0.80 0.19 0.09 0.50 2.90 6.30 4.30 0.65 bsc 1.00 ref 1.20 0.15 1.05 0.30 0.20 0.75 3.10 6.50 4.50 0.90 0.60 3.00 6.40 4.40
cat5112 http://onsemi.com 9 package dimensions msop 8, 3x3 case 846ad issue o e1 e a2 a1 e b d c a top view side view end view l1 l2 l detail a detail a notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec mo-187. symbol min nom max a a1 a2 b c d e e1 e l 0o 6o l2 0.05 0.75 0.22 0.13 0.40 2.90 4.80 2.90 0.65 bsc 0.25 bsc 1.10 0.15 0.95 0.38 0.23 0.80 3.10 5.00 3.10 0.60 3.00 4.90 3.00 l1 0.95 ref 0.10 0.85
cat5112 http://onsemi.com 10 table 7. ordering information device order number specific device marking package type temperature range lead finish shipping ? cat5112vi ? 10 ? gt3 cat5112v soic ? 8 ? 40 ? c to +85 ? c nipdau tape & reel, 3,000 units / reel cat5112vi ? 50 ? gt3 cat5112v soic ? 8 ? 40 ? c to +85 ? c nipdau tape & reel, 3,000 units / reel cat5112vi ? 00 ? gt3 cat5112v soic ? 8 ? 40 ? c to +85 ? c nipdau tape & reel, 3,000 units / reel cat5112yi ? 10 ? gt3 a22 tssop ? 8 ? 40 ? c to +85 ? c nipdau tape & reel, 3,000 units / reel cat5112yi ? 50 ? gt3 a24 tssop ? 8 ? 40 ? c to +85 ? c nipdau tape & reel, 3,000 units / reel cat5112yi ? 00 ? gt3 a25 tssop ? 8 ? 40 ? c to +85 ? c nipdau tape & reel, 3,000 units / reel cat5112zi ? 10 ? gt3 abpn msop ? 8 ? 40 ? c to +85 ? c nipdau tape & reel, 3,000 units / reel cat5112zi ? 50 ? gt3 abpn msop ? 8 ? 40 ? c to +85 ? c nipdau tape & reel, 3,000 units / reel cat5112zi ? 00 ? gt3 abpn msop ? 8 ? 40 ? c to +85 ? c nipdau tape & reel, 3,000 units / reel cat5112li ? 10 ? g cat5112l pdip ? 8 ? 40 ? c to +85 ? c nipdau rail, 50 units cat5112li ? 50 ? g cat5112l pdip ? 8 ? 40 ? c to +85 ? c nipdau rail, 50 units cat5112li ? 00 ? g cat5112l pdip ? 8 ? 40 ? c to +85 ? c nipdau rail, 50 units ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. 10. for detailed information and a breakdown of device nomenclature and numbering systems, please see the on semiconductor device nomenclature document, tnd310/d, available at www.onsemi.com on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 cat5112/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
|
